A FIFO (first-in-first-out) buffer functions as a shift register having an additional control section that permits input data to "fall through" to the first vacant stage. In other words, if there is data stored in the FIFO buffer, it is available at the output even though all of the stages are not filled. Thus, in effect, a FIFO buffer functions as a "variable-length" shift register, the length of which is always the same as the data stored therein. Although shift registers may be used, of late, many FIFO buffers are implemented with a dual port, random access memory (RAM) array, a write counter, and a read counter. The write counter is configured to develop, at the write data address inputs of the RAM array, signals representing a write pointer address; and, the read counter is configured to develop, at the read data address inputs of the RAM array, signals representing a read pointer address.
Many applications, including laser printer applications, require that the format of data stored in the FIFO buffer be converted from parallel to serial format. Of course, circuitry is available which will perform the necessary parallel-to-serial format conversion. Unfortunately, the use of additional circuitry adds to the system cost and complexity.
In the U.S. Pat. No. 4,750,149 of Michael Miller a "Programmable FIFO Buffer" device is disclosed which includes a number of multiplexers and flip-flops configured to convert from parallel-to-serial format, data stored in a FIFO buffer. The multiplexers and flip-flops are so configured as to permit the word length (number of bits) to be externally programmed. In addition, the multiplexers and flip-flops are so configured as to permit the use of the device with a similar device for word expansion. Unfortunately, the above mentioned device requires that a relatively large number of device pins be employed.